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agilent HDMP-0552 quad port bypass circuit with cdr and data valid detection for fibre channel arbitrated loops data sheet features ? supports 1.0625/2.125 gbd fibre channel operation quad pbc/cdr in one package cdr location determined by choice of cable input/output amplitude valid detection on fm_node[0] input data valid detection on fm_node[0] input ? run length violation detection ? comma detection ? configurable for both single- frame and multi-frame detection speed select pin for 1 or 2 gbd operation single refclk for 1 or 2 gbd operation cdr selectable via external pin enable/disable equalizers on all inputs enable/disable selected high- speed output drivers high speed lvpecl i/o buffered line logic (bll) outputs (no external bias resistors required) 1.1 w typical power at v cc = 3.3 v advanced 0.35 bicmos technology 64 pin, 10 mm, low cost plastic qfp package applications raid, jbod, bts cabinets 1=> 1-4 serial buffer with or without cdr description the HDMP-0552 is a quad port bypass circuit (pbc) with clock and data recovery (cdr) and data valid detection capability included. see figure 1 for block diagram. this device minimizes part count, cost and jitter accumulation while repeating incoming signals. port bypass circuits are used in hard disk arrays constructed in fibre channel arbitrated loop (fc-al) configurations. by using port bypass circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. a pbc consists of multiple 2:1 multiplexers daisy chained along with a cdr. each port has two modes of operation: disk in loop and disk bypassed. when the disk in loop mode is selected, the loop goes into and out of the disk drive at that port. for example, data goes from the HDMP-0552s to_node[n] differential output pins to the disk drive transceiver ic (for example, an hdmp-263x) rx differential input pins. data from the disk drive transceiver ic tx differential output pins goes to HDMP-0552s fm_node[n] differential input pins. figure 2 and figure 3 show connection diagrams for disk drive array applications. when the disk bypassed mode is selected, the disk drive is either absent or nonfunctional, and the loop bypasses the hard disk. multiple HDMP-0552s may be cascaded or connected to other members of the hdmp-04xx family through the fm_loop and to_loop pins to create loops for arrays of disk drives greater than 4. see table 3 to identify which of the 5 cells (0:4) provides fm_loop, to_loop pins (cell connected to cable). caution: as with all semiconductor ics, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (esd).
2 combinations of quad pbcs can be utilized to accommodate any number of hard disks. the unused cells in a quad may be bypassed with pulldown resistors on the bypass[n]- pins for these cells. additional power savings possible by turning off unused output drives. please refer to bll output section on page 3. an HDMP-0552 can be wired as a single or double mux cell with a cdr. it may also be used as a single or double mux cell without a cdr. all to_node outputs of the HDMP-0552 are of equal strength. therefore, this part may be used as a 1=>1- 4 buffer. the design of HDMP-0552 allows for placement of the cdr at any location with respect to hard disk slots. for example, if bypass[0]- pin is tied to v cc and hard disk slots a to d are connected to pbc cells 1 to 4 in the same order, the cdr function is performed at entry to the HDMP-0552 (figure 2). to achieve a cdr function at exit from the HDMP-0552, bypass[1]- must be tied to v cc and hard disk slots a to d must be connected to pbc cells 2, 3, 4, 0 in that order (figure 3). table 3 shows all possible connections. in case of cdr at entry, a signal detect (sd) pin shows the status of the signal at the incoming cable. the recommended method of setting the bypass[i]- pins high is to drive them with a high-impedance signal. internal pull-up resistors force the bypass[i]- pins to v cc . HDMP-0552 block diagram cdr the clock and data recovery (cdr) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. an automatic locking feature allows the cdr to lock onto the input data stream without external training controls. it does this by continually frequency locking onto the reference clock (refclk) and then phase locking onto the input data stream. once bit-locked, the cdr generates a high-speed sampling clock. this clock is used to sample or repeat the incoming data to produce the cdr output. the cdr jitter specifications listed in this data sheet assume an input that has been 8b/10b encoded. data valid output the outgoing data from the cdr is checked for two types of errors. first, the data is checked for run length violations (rlv), which are defined as a consecutive bit sequence greater than five. in addition, the data is checked for no comma detected (ncd), which is defined as no comma within a 2 15 bit frame. if neither of these errors occur, the data is considered valid fibre channel data, and fm_node[0]_dv is driven high. for reporting errors, the data valid (dv) block contains a 2 15 - bit counter to provide a frame clock. all errors are reported relative to the rising edge of this internally generated clock. there are two lvttl inputs for configuring the data validity checking. when mode_dv is high, the data input for the cdr comes from fm_node[0]. in this mode, the fm_node[0] input is checked for data validity. in addition, the fm_node[0]_dv lvttl output can be used to drive bypass[0]- signal. in this configuration, when the data is invalid, the cdr output will be bypassed and the data from to_node[0] will be passed on instead. when mode_dv is low, the data validity checking is still taking place on output of the cdr; however, this data may be from another input besides fm_node[0]. in addition, the cdr output data will always be passed on to to_node[1] in this mode. lastly, the lvttl input fsel selects single versus multi-frame operation of the dv block. for example, when fsel is low, the fm_node[0]_dv output will be driven high after 2 15 bits of good data. similarly, fm_node[0]_dv will be driven low after one 2 15 bit sequence containing errors. this is single frame operation. when fsel is high, the dv block is operating in multi-frame, or four frame, mode. in this mode, the fm_node[0]_dv will be driven high only after four consecutive frames of valid data. once high, fm_node[0]_dv will only be driven low after four consecutive 2 15 -bit frames containing errors. refclk input and ref_rate control the lvttl refclk input provides a reference oscillator for frequency acquisition of the cdr. the refclk frequency should be 53.125 mhz or 106.25 mhz +100 ppm. set ref_rate = 0 for a 53 mhz and set ref_rate = 1 for 106 mhz references. either reference frequency can be used for both 1 gbd or 2 gbd rates. amplitude valid output the amplitude valid (av) block detects if the incoming data on fm_node[0] + is valid by examining the differential amplitude of that input. the incoming data is considered valid and fm_node[0]_av is driven high, as long as the amplitude is greater than 200 mv (differential peak-to-peak). fm_node[0]_av is driven low as long as the amplitude of the input signal is less than 100 mv (differential peak-to-peak). when the amplitude of the input signal is between 100 and 200 mv (differential peak-to- peak), fm_node[0]_av is unpredictable.
3 equalizer input all fm_node[n] + high-speed differential inputs have an equalization setting to offset the effects of skin loss and dispersion on pcbs. this function is independently controllable for each input port using the eq_sel and ndx (x = 0-4) pins. the default setting for the equalization is true. equalization maybe set to fault for individual inputs by forcing eq_sel low and ndx (where x = port number) low for each port that the equalization setting is desired to be false. it is a logic or function. for instance, forcing eq_sel, nd2 & nd3 pins low will turn off the equalization setting at fm_node[2] + and fm_node[3] + while the equalization setting will remain on for ports 0, 1 and 4. the eq_sel and ndx (x = 0-4) pins are lvttl and contain internal pull-up circuitry. to force a pin low each pin should be connected to gnd through a 1 k w resistor. otherwise, these inputs should be left to float. in this case, the internal pull-up circuitry will force them high. bypass[n]- input the active low bypass[n]- inputs control the data flow through the HDMP-0552. all bypass pins are lvttl and contain internal pull-up circuitry. to bypass a port, the appropriate bypass[n]- pin should be connected to gnd through a 1 k w resistor. otherwise, the bypass[n]- inputs should be left to float. in this case, the internal pull-up circuitry will force them high. figure 1 - block diagram of HDMP-0552 bll output all to_node[n]+ high-speed differential outputs are driven by a buffered line logic (bll) circuit that has on-chip source termination. therefore, no external bias resistors are required. the bll outputs on the HDMP-0552 are of equal strength. unused outputs should be turned off independently. this reduces power and reduces the potential for crosstalk effects caused by incorrect terminations. if the unused outputs are not turned off they should be differentially terminated. the value of the termination resistor should match the pcb trace differential impedance. each output port is set to active or inactive by the out_sel and ndx (x = 0-4) pins. to_node [1] fm_node [1] bypass [1] - to_node [2] fm_node [2] bypass [2] - to_node [3] fm_node [3] bypass [3] - to_node [4] fm_node [4] bypass [4] - to_node [0] fm_node [0] bll equ ttl 1 0 bll equ ttl 1 0 bll equ ttl 1 0 bll equ ttl 1 0 bll equ 1 0 0 1 0 1 cdr cpll mode_dv ttl cdr_sel ttl fm_node [0]_dv ttl dv ttl fsel sstl cdr_rate ttl ref_rate ttl refclk av ttl fm_node [0]_av ttl bypass [0] -
4 output port active is the default condition. each output port may be set to inactive by forcing out_sel low and ndx (where x = port number) low. it is a logic or function. for instance, forcing out_sel, nd1 & nd4 pins low will turn off output ports to_node[1] + and to_node[4] + while output ports 0,2 and 3 will remain on. when an output port is off both output terminals will pull high to approximately v cc . figure 2 - connection diagram for cdr at first cell figure 3 - connection diagram for cdr at last cell 1 0 bypass [1]- to_node [1] fm_node [1] cdr to_node [0] = to_loop fm_node [0] = fm_loop bypass [0]- = 1 serdes hard disk a serdes hard disk b serdes hard disk c serdes hard disk d 1 0 bypass [2]- to_node [2] fm_node [2] 1 0 bypass [3]- to_node [3] fm_node [3] 1 0 bypass [4]- to_node [4] fm_node [4] 12340 1 0 the out_sel and ndx (x = 0-4) pins are lvttl and contain internal pull-up circuitry. to force a pin low each pin should be connected to gnd through a 1 k w resistor. otherwise, these inputs should be left to float. in this case, the internal pull-up circuitry will force them high. 1 0 to_node [2] fm_node [2] cdr to_node [1] = to_loop fm_node [1] = fm_loop bypass [1]- = 1 serdes hard disk a serdes hard disk b serdes hard disk c serdes hard disk d 1 0 bypass [2]- to_node [3] fm_node [3] 1 0 bypass [3]- to_node [4] fm_node [4] 1 0 bypass [4]- to_node [0] fm_node [0] 1 0 12340 bypass [0]-
5 table 1 - pin definitions for HDMP-0552. refer to figure 4 for pin layout pin name pin pin type pin description mode_dv 24 i-lvttl data valid detect mode : to allow data valid detection, float mode_dv high. to configure chip for "cdr anywhere" capability, connect mode_dv to gnd through a 1 k w resistor. fsel 25 i-lvttl frame select: to configure single-frame operation of the data valid and amplitude valid detection circuits, connect fsel to gnd through a 1 k w resistor. to configure multi-frame (4-frame) operation of the data valid and amplitude valid detection circuits, float fsel high. fm_node[0]_dv 23 o-lvttl data valid: indicates valid fibre channel data on the fm_node[0] inputs when high. indicates either run length violation error or no comma detected when low. fm_node[0]_av 59 o-lvttl amplitude valid: indicates acceptable signal amplitude on the fm_node[0] inputs. to_node[0]+ to_node[0]- to_node[1]+ to_node[1]- to_node[2]+ to_node[2]- to_node[3]+ to_node[3]- to_node[4]+ to_node[4]- 57 56 32 31 35 34 44 43 47 46 hs_out serial data outputs: high-speed outputs to a hard disk drive or to a cable input. fm_node[0]+ fm_node[0]- fm_node[1]+ fm_node[1]- fm_node[2]+ fm_node[2]- fm_node[3]+ fm_node[3]- fm_node[4]+ fm_node[4]- 54 53 29 28 38 37 41 40 51 50 hs_in serial data inputs: high-speed inputs from a hard disk drive or from a cable output. bypass[0]- bypass[1]- bypass[2]- bypass[3]- bypass[4]- 55 30 36 42 49 i-lvttl bypass inputs: for "disk bypassed" mode, connect bypass[n]- to gnd through a 1 k w resistor. for "disk in loop" mode, float high. cdr_sel 10 i-lvttl cdr select: to configure the chip with the cdr bypassed, connect cdr_sel to gnd through a 1 k w resistor. to configure the chip with the cdr in the loop, float cdr_sel high. cdr_rate 11 i-sstl2 cdr rate: to configure the chip for 1 gbd operation, connect cdr_rate to gnd through a 1 k w resistor. to configure the chip for 2 gbd operation, float cdr_rate high. ref_rate 12 i-lvttl reference rate: float ref_rate high for a reference rate of 106.25 mhz and connect ref_rate to gnd via a 1 k w resistor for a reference rate of 53.125 mhz. refclk 14 i-lvttl reference clock: a user-supplied clock reference used for frequency acquisition in the clock and data recovery (cdr) circuit. cpll1 cpll0 16 17 c c loop filter capacitor: a loop filter capacitor for the internal clock and data recovery (cdr) circuit must be connected across the cpll1 and cpll0 pins. recommended value is 0.1 f. eq_sel 61 i-lvttl equalizer select: allows user to select/deselect equalization on any input.
6 table 1 (continued) - pin definitions for HDMP-0552. refer to figure 4 for pin layout pin name pin pin type pin description out_sel 60 i-lvttl output select: allows user to turn on/off any output driver. nd0 64 i-lvttl node 0 input: in combination with eq_sel, allows the user to select/deselect equalization on fm_node[0] inputs. in combination with out_sel, allows the user to turn on/off the to_node[0] output driver. float high to select node 0, or connect to gnd through a 1 k w resistor to deselect node 0. nd1 63 i-lvttl node 1 input: in combination with eq_sel, allows the user to select/deselect equalization on fm_node[1] inputs. in combination with out_sel, allows the user to turn off/on the to_node[1] output driver. float high to select node 1, or connect to gnd through a 1 k w resistor to deselect node 1. nd2 62 i-lvttl node 2 input: in combination with eq_sel, allows the user to select/deselect equalization on fm_node[2] inputs. in combination with out_sel, allows the user to turn off/on the to_node[2] output driver. float high to select node 2, or connect to gnd through a 1 k w resistor to deselect node 2 . nd3 20 i-lvttl node 3 input: in combination with eq_sel, allows the user to select/deselect equalization on fm_node[3] inputs. in combination with out_sel, allows the user to turn off/on the to_node[3] output driver. float high to select node 3, or connect to gnd through a 1 k w resistor to deselect node 3. nd4 21 i-lvttl node 4 input: in combination with eq_sel, allows the user to select/deselect equalization on fm_node[4] inputs. in combination with out_sel, allows the user to turn off/on the to_node[4] output driver. float high to select node 4, or connect to gnd through a 1 k w resistor to deselect node 4. tdo 2 o-lvttl jtag tdi 3 i-lvttl jtag ntrst 4 i-lvttl jtag tms 5 i-lvttl jtag tck 6 i-lvttl jtag nc 19 nc no connect. gnd 07 09 15 18 26 39 52 s ground: normally 0 v. v cc 01 13 22 27 48 s digital power supply pin. v cc a 08 s analog power supply pin. v cc hs 33 45 58 s s s cells 1 and 2 high speed output pins power supply. cells 3 and 4 high speed output pins power supply. cell 0 high speed output pins power supply.
7 figure 4 - HDMP-0552 package layout and marking, top view xxxxxxx-nn = wafer lot - build number; s = supplier code; yyww = date code (yy = year, ww = work week); rz.zz = die revision; country (on back side) = country of manufacture. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vcc to_node [4] + to_node [4] - vcchs to_node [3] + to_node [3] - bypass [3] - fm_node [3] + fm_node [3] - gnd fm_node [2] + fm_node [2] - bypass [2] - to_node [2] + to_node [2] - vcchs vcc td0 td1 ntrst tms tck gnd vcca gnd cdr_sel cdr_rate ref_rate vcc refclk gnd cpll1 nd0 nd1 nd2 eq_sel out_sel fm_node [0]_av vcchs to_node [0] + to_node [0] - bypass [0] - fm_node [0] + fm_node [0] - gnd fm_node [4] + fm_node [4] - bypass [4] - to_node [1] + to_node [1] - bypass [1] - fm_node [1] + fm_node [1] - vcc gnd fsel mode_dv fm_node [0]_dv vcc nd4 nd3 nc gnd cpll0 agilent HDMP-0552 xxxxxxx-nn s yyww rz.zz
8 table 2 - i/o type definitions please refer to figures 5 and 6 for simplified i/o diagrams. table 3 - pin connection diagram to achieve desired cdr location x denotes cdr position with respect to hard disks. for example a x b c d means the cdr is between disk a and disk b. HDMP-0552 electrical specifications absolute maximum ratings ta = +25 c , except as specified. operation in excess of any of these conditions may result in permanent damage to this device. figure 5 - simplified digital i/o circuit diagrams hard disks a b c d a b c d a b c d a b c d a b c d connection to pbc cells 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 cdr position (x) x a b c d a x b c d a b x c d a b c x d a b c d x cell connected to cable 0 4 3 2 1 i/o type definition i-lvttl lvttl input o-lvttl lvttl output hs_out high speed output, bll hs_in high speed input c external circuit node s power supply or ground nc no connect i-sstl2 sstl2 compatible, non-terminated symbol parameter units minimum maximum vcc supply voltage v -0.7 4.0 vin, lvttl lvttl input voltage v -0.7 5.0 vin,hs_in hs_in input voltage v 2.0 vcc io,lvttl lvttl output current ma +13 tstg stor age tempera tur e c -65 +150 tj junction temperature c0 +125 vdd gnd o output gnd i input gnd vdd
9 guaranteed operating rates ta = 0 c to tc = +80 c , vcc = 3.15 v to 3.45 v figure 6 - o-bll and i-bll simplified circuit schematic clock and data recovery circuit (cdr) reference clock requirements ta = 0 c to tc = +80 c , vcc = 3.15 v to 3.45 v dc electrical specifications ta = 0 c to tc = +80 c , vcc = 3.15 v to 3.45 v note: 1. lvttl i/os 5 v tolerant. symbol parameter units minimum typical maximum f nominal frequency (ref_rate = 1) mhz 106.25 f nominal frequency (ref_rate = 0) mhz 53.125 ftol frequency tolerance ppm -100 +100 symm symmetry (duty cycle) % 40 60 symbol parameter units minimum typical maximum vih 1 ,lvttl lvttl input high voltage range v 2.0 vcc vil,lvttl lvttl input low voltage range v 0 0.8 voh 1 ,lvttl lvttl output high voltage range, ioh = -400 ua v 2.2 vcc vol,lvttl lvttl output low voltage level, iol = 1 ma v 0 0.6 iih,lvttl input high current (magnitude), vin = 2.4 v, vcc = 3.45 v ua 0 5 40 iil,lvttl input low current (magnitude), vin = 0.4 v, vcc = 3.45 v ua 0 65 300 icc total supply current, ta = +25 cma320 serial clock rate fc (mbd) minimum maximum 1,040 1,080 2,080 2,160 zo = 75 w zo = 75 w 2 x zo = 150 w hs_out gnd esd protection 75 w v cc hs v cc gnd +to_node -to_node hs_in gnd esd protection v cc v cc gnd +fm_node -fm_node 0.01 f 0.01 f + - + - note: hs_in inputs should never be connected to ground as permanent damage to the device may result.
10 ac electrical specifications ta = 0 c to tc = +80 c , vcc = 3.15 v to 3.45 v note: 2. measured from 20% to 80% levels with trace length 3", fr-4 board, zo= 50 ohms and a 50 ohm and 200 ff termination. please refer to figure 6 for simplified circuit schematic. power dissipation and thermal resistance ta = 0 c to tc = +80 c , vcc = 3.15 v to 3.45 v output jitter characteristics ta = 0 c to tc = +80 c , vcc = 3.15 v to 3.45 v please refer to figures 8 and 9 for jitter measurement setup information. figure 7 - eye diagram obtained differentially at 2.125 gbd from node(0) to node(2) with 50 w termination symbol parameter units typical maximum pd power dissipation w 1.1 1.28 q jc thermal resistance, junction to case c/w 2.5 symbol parameter units typical rj random jitter at to_node pins (1 sigma rms) ps 3.5 dj deterministic jitter at to_node pins (pk-pk) ps 10 symbol parameter units minimum typical maximum tdelay1 total loop latency from fm_node[0] to to_node[0] ns 1.5 4.0 tdelay2 per cell latency from fm_node[x] to to_node[x+1] ns 0.4 0.8 tr,lvttlin input lvttl rise time requirement, 0.8 v to 2.0 v ns 2 tf,lvttlin input lvttl fall time requirement, 2.0 v to 0.8 v ns 2 tr, lvttlout output lvttl rise time range, 0.8 v to 2.0 v, 10 pf load ns 1.5 tf, lvttlout output lvttl fall time range, 2.0 v to 0.8 v, 10 pf load ns 2.0 trs 2 ,hs_out hs_out single-ended rise time ps 44 65 110 tfs 2 ,hs_out hs_out single-ended fall time ps 44 65 110 trd 2 ,hs_out hs_out differential rise time ps 44 65 110 tfd 2 ,hs_out hs_out differential fall time ps 44 65 110 vip,hs_in hs_in input peak to peak required differential voltage range mv 200 2000 vop,hs_out hs_out output pk-pk diff. voltage range (zo = 75 w ) mv 1100 1400 2000
11 locking characteristics ta = 0 c to tc = +80 c , vcc = 3.15 v to 3.45 v figure 8 - setup for measurement of random jitter figure 9 - setup for measurement of deterministic jitter parameter units maximum bit sync time (phase lock) bits 2500 frequency lock at powerup s 500 70841b pattern generator data clock k28.7 0011111000 70311a clock source 2.125 ghz 1/20 variable delay bias 1.4 106.25 mhz HDMP-0552 fm_node[0] ref clk bypass - [0] bypass - [1] bypass - [2] bypass - [3] bypass - [4] to_node[1] 83480a digital communication analyzer trigger ch 1/2 v cc 2 2 random jitter 70841b pattern generator data clock +k28.5 -k28.5 70311a clock source 2.125 ghz 1/20 variable delay bias 1.4 106.25 mhz HDMP-0552 fm_node[0] ref clk bypass - [0] bypass - [1] bypass - [2] bypass - [3] bypass - [4] to_node[1] 83480a digital communication analyzer trigger ch 1/2 v cc 2 2 deterministic jitter 1/2
www.semiconductor.agilent.com data subject to change. copyright ? 2001 agilent technologies, inc. october 15, 2001 5988-3998en package information mechanical dimensions figure 10 - HDMP-0552 package drawing dimensional parameter (millimeters) aa1a2d/ed1/e1l b c e value 2.45 0.25 2.00 13.20 10.00 0.88 0.22 0.17 0.50 tolerance max min +0.10, -0.05 0.25 0.10 +0.15, -0.10 0.05 max basic pin no. 1 id e1 e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 top view d d1 a2 a1 a seating plane b e l c 0.25 gauge plane item details package material plastic lead finish material 85% tin, 15% lead lead finish thickness 300-800 micro-inches lead skew 0.08 mm maximum lead coplanarity (seating plane method) 0.08 mm maximum

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